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| W3A43G104ZAT2A資料 | |
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W3A43G104ZAT2A PDF Download |
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File Size : 116 KB
Manufacturer:AVX Description:Data inputs for a 18-bit bus. MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master Reset, the FIFO is configured for either FWFT or IDT Standard mode, one of two program mable flag default settings, and serial or parallel programming of the offset settings. PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset, the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings are all retained. RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to HIGH in FWFT mode) temporarily and does not disturb the write pointer, programming method, existing timing mode or programmable flag settings. RT is useful to reread data from the first physical location of the FIFO. During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin functions as a serial input for loading offset registers |
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| 1PCS | 100PCS | 1K | 10K | ||
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型 號：W3A43G104ZAT2A 廠 家：AVX 封 裝：06+ 批 號：SMD 數(shù) 量：120000 說 明：【自己庫存】 |
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